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AMD’s Venice-X maxes out family at 5.3 GHz, returning 3D V-Cache to data center after four years
Venice-X maxes out the family's frequency for the first time.
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AMD missed out on deploying Turin-X CPUs in the previous generation, giving its 3D V-Cache tech a four-year hiatus from the data center following the launch of Genoa-X in 2023. In the second half of next year, 3D V-Cache is coming back for HPC with Venice-X, matching the 96 cores and 1,152 MB of L3 cache available on the EPYC 9684X (Genoa-X), but with vastly higher clock speeds, PCIe 6.0, and nearly four times the per-socket memory bandwidth.
After first bringing hybrid bonding to EPYC processors with Milan-X in 2022, AMD followed up a little over a year later with Genoa-X. Turin came and went without a chip sporting stacked SRAM, but now, it’s back with Venice-X. The critical change this time around doesn’t come from big jumps in core count — and consequently cache — as is the case with the standard SP7 lineup. Rather, it’s the 5.3 GHz boost clock speed, another pillar of Venice broadly, that’s particularly beneficial in the HPC workloads Venice-X targets.
As you can see from the top EPYC -X chips from previous generations, boost clocks were significantly lower for the X chips, and higher frequencies were available within the standard chips from each family. Milan scaled up to 4.1 GHz, while Genoa could climb to 4.4 GHz, just not on the EPYC -X chips. Venice-X brings up to the maximum 5.3 GHz boost clock available across the range, unifying a high frequency with a large pool of bonded L3 for HPC workloads.
There are still details missing about Venice-X, including the base frequency, how many SKUs are in the lineup and what their specs are, and the TDP (though the 400 to 600 W range available to other Venice CPUs is likely). The chips appear to use the SP7 socket, however, keeping with previous EPYC -X chips.
The platform comes with 96 PCIe 6.0 lanes, while the smaller SP8 platform targeting enterprises trades memory channels for PCIe lanes. Venice-X comes with the full 16-channel memory setup available on SP7, including support for MRDIMMs at 12,800 MT/s that can drive the quoted 1.6 TB/s of per-socket memory bandwidth.
The critical marriage with Venice-X for HPC workloads, according to AMD, is high frequency with a large pool of stacked cache. AMD currently maintains both 3D V-Cache and high-frequency EPYC chips in its HPC fleet to run its internal EDA workloads. AMD Fellow Phil Steinke says the company runs performance analysis on these workloads to characterize performance, optimize EPYC designs, and push partners to optimize their software.
The biggest consumer on the HPC fleet by far are function verification workloads at over half of AMD's used compute, according to Steinke. These are logic simulations that show up in tools like Cadence Xcelium, and Steinke says the EPYC team is running these workloads “24 x 7 x 365.”
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