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Researchers allege DeepSeek, Kimi, and other Chinese AI models were trained using banned Nvidia Blackwell GPUs
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The topic of U.S. trade controls precluding the export of Nvidia and AMD high-end AI accelerator chips to China has taken a few twists lately. Jensen Huang's affairs aside, it's an open secret in the industry that Nvidia's Blackwell silicon finds its way into China, whether physically or virtually. UnemploymentLabs, an independent research outfit, has come up with strong evidence that those chips were used for training open-weight Chinese AI models, including DeepSeek V4, Kimi K3.1, MiniMax-M3, and Ling-3.1-Flash.
The scientists are careful to hedge their findings, noting that while their math checks out, it does not reveal where the chips were, how they were accessed, or prove that export controls were broken. As far as we can tell, it's currently not illegal for Chinese companies to rent Blackwell hardware abroad, and even though Nvidia's grip is tightening, U.S. companies aren't strictly prohibited from doing so, as evidenced by the recent Tencent-Oracle deal.
This identification method is limited to models with open weights, and depends on both hardware and software stacks used for model training — and yet it's both clever and simple, like the Egg of Columbus.
Let's establish some base facts. First, different AI accelerator families have unique counts of shader modules (SMs), marginally analogous to CPU cores — Nvidia's Hopper chips have 132, Blackwell B series have 148, and Blackwell GBs come with 152. Second, while there's more than one software stack for training AI models, PyTorch and its CUDA-aware friends are by far the most widely used on the green team's hardware.
The first step for training a model is initializing its weights, or how strongly the model considers each individual input. In modern LLM architectures, their initialization goes through a randomization step in which their values are adjusted plus/minus pseudo-randomly, using cuRAND — as in, randomly, but a seed starting value results in the same adjustment figures every time.
As you'd expect, doing this for an entire model is a lot of computational work, so this process is spread out across all the SMs, further subdivided into threads. For large weight sets, the thread count per SM is 2,048 for Blackwell and Hopper silicon, and it's surely carefully chosen and optimized for.
The researchers repeated a facsimile of the initialization process using the same chips, software, and thread counts. Using relatively simple statistical analysis, they spotted that their final statistical distribution of weight values precisely matched that of DeepSeek, Kimi, et al. As a test, they changed the SM and thread counts, and predictably, the correlation completely broke down.
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This let them pick out each family of Blackwell/Hopper chip used for each model, and eventually they also figured out an approximate count of cards used. They cannot, however, pinpoint which exact variation produced the weights, as this analysis is linked to initialization layout counts alone, thus SM count and usage pattern — not to VRAM capacity, memory bandwidth, or other characteristics that distinguish individual cards.