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Hot Chips 2026: OpenAI's Jalapeño AI ASIC unpacked — accelerator developed using AI achieves efficiency and throughput gains against power-hungry Blackwell
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OpenAI made quite a splash back in June, when it unveiled its 'Jalapeño' AI accelerator and revealed that the chip reached tape-out in just nine months. At the Hot Chips conference, OpenAI disclosed more details about the architecture of its Jalapeño inference processor as well as shared its target and real-world performance numbers. The company claims its NUMA-style spatial architecture enables Jalapeño to outperform Nvidia's GB200 and GB300 in low-latency inference and in terms of performance-per-watt, while a 2,048-processor system scales to 27 exaFLOPS and 32 PB/s of aggregate memory bandwidth.
OpenAI's Jalapeño is a massive AI inference accelerator co-developed with Broadcom, with 216 GB of HBM4 memory and up to 15.4 TB/s of bandwidth. The processor delivers up to 3.4 MXFP8 PFLOPS as well as up to 13.4 MXFP4 PFLOPS at 700W, which makes it suitable for inference, though the MXFP4 format may not be enough for training. The ASIC has a 700W power rating and operates at 1.70 GHz on silicon already running in OpenAI's labs, though OpenAI's engineers said at Hot Chips that the plan is to increase clocks up to 1.80 GHz, perhaps to get higher peak performance.
On the scalability side of matters, Jalapeño can scale to 128 accelerators in a local rack interconnected using Ethernet at 600 GB/s and to 2,048 ASICs in a 16-rack pod configuration at 200 GB/s per processor. The complete system offers 27 EFLOPS of MXFP4 performance, 432 TB of HBM4 memory, and 32 PB/s of aggregate memory bandwidth. For connectivity, OpenAI uses Broadcom Tomahawk 6 Ethernet switches and what it calls a 'half-flattened' two-level Clos topology that provides higher bandwidth for tensor-parallel traffic, lower bandwidth for expert-parallel communication, and prioritizes low latency for both. During the Q&A session, OpenAI confirmed that the scale-up network uses Ethernet with 200-Gb/s links. Jalapeño's physical hardware around the Broadcom-made chip is set to be made by Celestica.
On paper, Jalapeño's specifications look good, but they barely look impressive compared to Nvidia's Blackwell Ultra accelerators (10 FP8 PFLOPS, 20/15 sparse/dense NVFP4 PFLOPS). However, OpenAI argues that raw compute and memory bandwidth are not what makes its Jalapeño platform different.
The company says a 128-ASIC Jalapeño domain has more than 1 PB/s of aggregate HBM4 bandwidth, which is significantly higher compared to GB300 NVL72 (576 TB/s). A one-trillion-parameter model using FP4 weights requires about 0.5 TB. So, purely from a bandwidth perspective, the system could read the entire model more than 2,000 times per second. Meanwhile, actual inference performance comes nowhere near that theoretical ceiling, which is why hardware developers do not tend to add HBM bandwidth infinitely.
Instead, Jalapeño uses what OpenAI describes as a memory-sliced, or NUMA-style, architecture. The chip has 64 core slices, and each of them is paired with its own HBM slice to guarantee predictable latency and bandwidth. OpenAI says this arrangement avoids conflicts associated with a unified memory subsystem and lets frequently used operands remain close to the compute resources that need them. OpenAI does not explain why it chose exactly 64 slices, which likely means it was a sweet spot for the current architecture.
To connect the 64 core slices, OpenAI uses a specialized high-bandwidth, low-latency collective network that moves data coupled to compute operations 'register-to-register, with zero conflicts' in a bid to eliminate several performance bottlenecks. In addition, Jalapeño has a separate general-purpose network-on-chip (NoC) that handles less common communication (e.g., remote/global memory accesses) and provides access to the external scale-up network.
The distinction between these fabrics is substantial. OpenAI describes the general NoC as deliberately more 'anemic than you woul