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Nuvacore reveals unconventional Core First CPU IP design strategy
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When Nuvacore, a new CPU startup founded by legendary CPU and system architects Gerard Williams, John Bruno, and Ram Srinivasan, emerged from stealth earlier this year, it promised to "rewrite the rules of silicon," but did not say how it planned to do so. On Thursday, the company finally broke its silence and revealed that it is taking an unusual development approach that allows it to design a significant portion of its CPU core IP before committing to a particular instruction set architecture (ISA).
Traditionally, CPU developers start development of a new processor project with a particular ISA — such as Arm, RISC-V, or x86 — already selected. Although modern high-performance processors translate instructions into internal micro-operations and therefore separate the ISA from much of the underlying execution pipelines, the instruction set still influences numerous architectural decisions, including instruction decoding, register handling, memory ordering, and, of course, software compatibility.
Nuvacore says its Core First approach reverses at least part of this process. Instead of designing WarpCore around the requirements and limitations of a predetermined ISA, the company's engineers are developing a significant portion of the foundational CPU IP independent of a particular ISA. To a large degree, one can compare such an approach to the development of a car around its engine and not trying to fit an engine into an already developed platform.
"Rather than beginning with the constraints of an existing architecture and iterating from there, we are starting with the core itself," the company said in its statement.
As a result, the team may be able to better focus on the core's microarchitecture and optimize it for performance, power efficiency, and sustained workloads typical of modern data centers and AI infrastructure, the target application for the company. Nuvacore intends to select an instruction set later based on what works best for the systems that it and its partners plan to build.
There are obvious limits to how ISA-independent a CPU design can be. Eventually, WarpCore will need front-end logic designed around its chosen instruction set, and those architectural requirements will inevitably affect other parts of the processor. Nevertheless, substantial pieces of a modern CPU — such as execution units, branch-prediction units, data paths, caches, and portions of the memory subsystem — can be developed and evaluated before every ISA-related implementation decision is finalized.
In addition to not disclosing its ISA, which is arguably the biggest unanswered question surrounding the project, Nuvacore also has not disclosed the project's schedule, configuration, manufacturing process, power, or performance targets, though given the lack of the ISA commitment, one could say that the remaining details are not that important.
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For now, the only thing that Nuvacore discloses about WarpCore is that it is "a new class of general-purpose CPU designed specifically for the sustained performance and power-efficiency requirements of AI infrastructure and contemporary data centers."