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Tesla unveils AI accelerator roadmap, adopts new 'SI' branding in 'Super Intelligence' push
Adopts 'Super Intelligence' term for new processors, retrofits it for old ones too.
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Tesla has disclosed its revamped AI accelerator roadmap that sheds some light on the future of the company's chip development efforts. The Elon Musk company expects that its 6th Generation inference accelerator will bring 80X more compute performance than the existing 4th Generation chip, whereas its D3 training accelerator will cease to use SRAM-centric architecture in favor of a multi-chiplet design with stacked HBM. Also, Tesla has adopted the term "super intelligence" instead of artificial intelligence for its AI accelerators, renaming them with SI monikers. Musk recently confirmed SpaceXAI would be redubbed SpaceXSI for the same reason.
Wait a minute… I thought @elonmusk ’s Tesla chips were called AI4, AI5, and AI6.
But in this latest presentation, they’re now labeled SI4, SI5, and SI6.
Then I remembered: President Trump wants to replace “Artificial Intelligence” (AI) with “Super Intelligence” (SI).
Looks like Elon Musk may already be embracing the new terminology. 🤔November 4, 2026
Perhaps the most interesting development in Tesla's AI hardware roadmap is the re-emergence of the in-house developed Dojo training accelerator after Elon Musk cancelled the whole wafer-level Dojo project in August, 2025, and then said SpaceX and xAI would exclusively use Nvidia hardware in August, 2026, both in its terrestrial and extraterrestrial data centers. Yet, the 3rd Generation Dojo will be considerably different from the first two generations, Dojo D1 and Dojo D2.
Tesla describes its next-generation Dojo 3 (D3) training accelerator as a chiplet-based design that combines 2.5D and 3D packaging technologies with stacked HBM. This represents a substantial departure from the original Dojo D1 system-on-wafer architecture, which relied on distributed on-chip SRAM and interconnected 25 D1 processors with 11 GB of SRAM using wafer-scale packaging technology. The adoption of HBM suggests that Tesla intends to substantially increase memory capacity, as modern AI models consume extreme amounts of memory to store parameters, activations, and intermediate data, making SRAM unattractive from a capacity standpoint. The use of HBM simplifies memory scaling but introduces different latency, bandwidth, packaging, and power trade-offs. Yet, it remains unclear whether the company has abandoned wafer-scale integration altogether.
On the one hand, it is possible to stack custom HBM modules on top of logic dies interconnected using wafer-scale packaging technology. On the other hand, wafer-level integration is expensive and makes the most sense for select use cases, which include SRAM-centric architectures. Stacking HBM atop wafer-scale interconnected logic dies adds further design complexities, cooling challenges, manufacturing complexity (i.e., potentially reducing yields), long-term reliability concerns, and ultimately costs. While most of the challenges can be resolved by adding redundancy and refining process technologies, this all comes at a cost, making wafer-scaling less likely for D3.
Tesla has yet to disclose D3's compute performance, memory capacity, manufacturing process, or development schedule. At the same time, it claims that its Dojo D3 will be optimized for 'space, training, and scaling,' which means the unit will offer decent performance and will be easy to scale (which again points to a more conventional architecture of accelerators rather than to wafer-scale packaging). More intriguingly, the D3 is also set to be optimized for extraterrestrial deployments, which probably means radiation hardening for at least select SKUs.
Another interesting detail in the roadmap is the disclosure of approximate compute performance of Tesla's 6th Generation inference accelerator (SI6): 80X compute improvement over HW4 and 9X more memory over HW4. Depending on ho