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Micron details ambitious DRAM and NAND roadmap — 3D NAND, High-NA EUV, new materials, and custom silicon makes a comeback
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Last month, Micron disclosed its DRAM and NAND memory roadmaps for the next several years, revealing plans to use wafer bonding, new materials that enable making NAND cells smaller, High-NA EUV lithography, and detailing its moves toward 3D DRAM. Perhaps the most revealing part of Micron's story is that the company plans to expand its portfolio of custom DRAM and NAND products as AI developers increasingly require memory and storage solutions optimized for their unique processor architectures and specific workloads.
" DRAM is nearing atomic limits at this point: although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view," said Scott DeBoer, president and chief technology and products officer at Micron, at the company's event earlier this month. "[With 3D NAND, we are] really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward."
In a surprising move, Micron decided to abandon plans to produce DRAM with 4F2 memory cells, unlike its rivals at CXMT, Samsung, and SK hynix, citing the lack of a viable scaling path beyond where Micron is today. Instead, Micron's roadmap for the coming years includes wafer bonding, High-NA EUV lithography, new materials, and eventually 3D DRAM. The company plans to begin mass production of its next-generation 1δ memory in the second half of 2027, while subsequent 1ε, ζÅ, and ηÅ technologies are at various stages of development. In parallel, Micron is developing two generations of 3D DRAM that could eventually succeed conventional planar memory.
Micron's current 1γ (1-gamma) DRAM process technology, which is in high-volume manufacturing (HVM), is the company's first DRAM node to use EUV lithography. Previously, Micron had used multipatterning with DUV lithography and remained competitive with Samsung and SK hynix, which relied on EUV for critical layers.
Micron's next-generation 1δ (1-delta) fabrication process is currently in the yield ramp stage and is scheduled to enter mass production in the second half of 2027. The company expects the technology to increase bit density by mid-20% compared to 1γ, while advanced high-k metal gate (HKMG) CMOS, new materials, angstrom-level process control, and equipment intelligence should improve performance, power efficiency, and ultimately yields as well as costs.
Micron plans to manufacture 1δ DRAM in the U.S. and use the technology for next-generation DDR, LPDDR, graphics memory, HBM5, vertical HBM (vHBM), and vertical Edge Inference Memory (vEIM) products. Meanwhile, to make HBM5, vHBM5, and vEIM products, the node will also support additional features like through-silicon vias (TSVs) and other elements to improve thermal performance.
The subsequent 1ε (1-epsilon) process will rely on wafer bonding, which will enable Micron to produce different structures on separate wafers and then bond them together. This approach could increase flexibility in memory design and manufacturing, but Micron has yet to disclose its plans to implement wafer bonding, which structures it will bond, or what improvements in density, performance, and power consumption the technology will provide. The process is currently under development, and there is no announced production schedule.
Micron's ζÅ (zeta-angstrom) production node is currently in early development and will introduce High-NA EUV lithography to memory manufacturing, which will enable further reductions in critical dimensions. The company has not disclosed how many layers will require High-NA lithography, the expected density improvements, or when the technology will enter mass production. However, it is obvious that the node will not be here until at least 2030, years after Samsung and SK hynix adopt High-NA EUV at their DRAM fabs