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Qualcomm will license patents behind Huawei’s LogicFolding chip architecture, report says
How much logic is actually stacked inside Huawei’s Kirin 9050 Pro?
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Qualcomm has reached a deal to license Huawei patents behind the LogicFolding chip-stacking method, Bloomberg reports. The technology, which is used in the Kirin 9050 Pro, splits nearly every block across two bonded dies, and a teardown and die shots show the lower die holds mostly cache and I/O.
Qualcomm’s multiyear, cross-license deal with Huawei has a wide scope, covering 5G devices, AI services, near- and co-packaged optics and networks, a Huawei spokesperson told Bloomberg. Qualcomm also intends to purchase specific Huawei U.S. patents in compute, AI, networking, and other technologies, according to a release. Neither company’s announcement named any patents, LogicFolding, or any chip that uses it.
Bloomberg's report frames the deal as a win for Huawei, validating its chipmaking acumen. The deal remains subject to approval, and Qualcomm will reportedly pay Huawei to license its patents for the first time. According to the report, LogicFolding targets faster data transmission as a workaround for China’s lack of access to EUV lithography machines.
The Kirin 9050 Pro is used in the Huawei Mate XT 2 tri-fold smartphone, launched Sept. 7. Geekerwan, a Chinese tech review channel known for in-depth chip testing, had a lab slice the chip for its teardown. Kurnal, a semiconductor researcher who publishes die-shot analysis, also posted annotated shots of both dies on X. Geekerwan’s cross-section shows the two dies bonded face to face, and both show the execution units on top, with the PLLs also on the lower die.
Hisilicon Hi36E0(Kirin 9050) Dieshot
https://t.co/iKiY621Bmg https://t.co/qup0ANqYUEOctober 2, 2026
LogicFolding was first unveiled on May 25 by He Tingbo, president of Huawei’s semiconductor business, at IEEE ISCAS 2026 in Shanghai, under the company’s “Tau Scaling Law,” which uses signal delay rather than transistor size as a measure. Huawei describes both layers as active and working as one. Vertical interconnects work to create shorter signal paths, which can reduce energy consumption. Peking University’s “true 3D” design tool for the technology shows a 30% wire-length cut in its own tests.
Huawei’s papers describe a “Kirin 2026” chip whose figures match the Kirin 9050 Pro’s. In a paper last month, relayed by TrendForce, Huawei said the chip uses a 1.5-micrometer hybrid-bonding pitch with about 50 million interconnects. About 10–15% of those carry signals. Core routing is 20% shorter, with critical paths up to 70% shorter. Power is reduced by as much as 66% for NPU, 58% for GPU, and 41% for a CPU performance core at the same performance level. NPU performance holds 29 TOPS at 63% less frequency and at a lower voltage.
Huawei does not name a process node. On its roadmap is Kirin 2027 at a 1-micrometer pitch and more than 100 million interconnects; for around three years out, a 720-nanometer pitch with over 200 million. It is targeting a 1.4nm-class density by 2031, with LogicFolding in the Ascend 990 AI accelerator around 2030. HiSilicon, Huawei’s chip-design unit, designs the Kirin chips, and SMIC is believed to make them, according to Reuters via TrendForce. It isn’t stated who handles the bonding process.