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Cognichip reveals how its new AI-assisted program can slash chip design times from months to days — automating labor-intensive tasks cuts design time down, Chief Product Officer explains
We speak to Cognichip's Chief Product Officer, Stelios Diamantidis, about its new AI products
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Amid the AI gold rush, one particularly fruitful vein of research is the emergence of AI-assisted workflows in electronic design automation (EDA) tools like Cadence Maestro. One such company developing such foundational models is Cognichip, which in September launched Artificial Chip Intelligence (ACI), proprietary AI models developed specifically for semiconductor engineering. ACI deploys the 'industry’s largest training dataset' across semiconductor physics and chip design principles.
ACI Enterprise is Cognichip's deployable platform, which combines these specialized models with agentic workflows, project memory, and computing infrastructure for AI inference. The company describes ACI's approach as a self-learning flywheel, a continuously evolving design environment that brings together specifications, register-transfer level (RTL), and verification results to build a design that meets power, performance, and area (PPA) targets to Pareto limits. We sat down with Cognichip to learn more.
"We have surpassed, I think, over ten million training samples in our datasets that are either things that we designed ourselves directly or things that have been generated through our synthetic technology," says Stelios Diamantidis, Chief Product Officer at Cognichip, in an interview with Tom's Hardware Premium. "We have invented new ways of creating synthetic training samples for semiconductor design. And very importantly, now that we have all these data samples, characterized data samples, we also had to invent new models so that we can capture the data, and we also had to invent new pipelines for training so that we can map the training data to the models themselves."
Cognichip says ACI can analyze specifications, explore microarchitectural options, generate RTL, verify designs, identify and fix functional problems, and optimize designs to meet PPA targets. The system can also integrate existing IP modules and even produce FPGA implementations. In principle, ACI enables engineers to focus on product requirements and architectural decisions while ACI handles much of the logic implementation and verification work.
"Build the spec, build the RTL, estimate PPA, perform optimizations, run verification, everything," Diamantidis told us while explaining how ACI can develop and evaluate multiple architectural alternatives before engineers select the preferred design. "We do not try to turn the designer into a verification engine; our system is self-verified, so we want the designer to design, and we want our system not only to do the tasks but also verify them."
Because ACI operates as a self-learning flywheel, Cognichip claims engineers can revisit earlier architectural decisions and modify their designs without restarting the entire development process from scratch.
"Architecture, microarchitecture, RTL, all abstractions in the cognitive system are aligned, so the change in microarchitecture is essentially automatically reflected in RTL, and vice versa," Diamantidis explained. "Changes in RTL are automatically reflected in microarchitecture."
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