// HACKER NEWS — CYBERSECURITY
Spaghettifying DRAM
Unlocking everything on the CPU with DRAM scrambling — PSP, C6, microcode,
SMM, and anything else the specs left out.
Poke the DRAM controller and an address can be made to land wherever you
want in memory. skitter-creek-bath-salts reaches into the deepest level of
the memory hierarchy and rewires the physical DRAM address translations,
to scramble platform memory and release its most guarded secrets — the
specialized carveouts invisible even to the kernel. When the translations
break, the walls built on them collapse, and we unlock everything.
Developed and tested on AMD Family 16h CPUs, the last generation whose
datasheets document the DRAM controller's translation registers — and show that
they can't be locked. 17h and beyond simply leave this information out. The
odyssey of *p is similar across generations and
architectures, and the underlying transforms extend even to ARM, RISC-V, and
beyond; skitter-creek-bath-salts shows us only how to begin.
Memory is built on layers of abstraction so deep they become almost absurd. When
your code dereferences *p, it appears to access the DRAM at p. It does not —
p is a virtual address, and before a single bit of DRAM is touched, it must
survive the gauntlet below:
This project works at the deepest levels of the *p pipeline, the MCT/DCT layer
— where a physical address from the data fabric/interconnect enters the memory
controller and is rewritten one final time into the raw DRAM coordinates that are
issued to the DIMM.
Physical addresses are really more of a suggestion.
One bit-flip in the DRAM controller rewires the entire foundation of the *p
pipeline, and the data that was at &x is now somewhere else mid-flight.
Suddenly &x != &x. Every elaborate mechanism the CPU and firmware and
uncore and chipset have meticulously used to wall off all the most protected
regions of memory all sit above the memory controller, and are entirely
oblivious to anything that happens beneath it. All the existing memory fences
guard physical addresses, not DRAM coordinates, and if you rearrange the
DRAM coordinates, all the CPU and data fabric barriers above them are entirely
unaware.
But rewiring DRAM is easy. The bit above is the bank-swizzle-mode in the DCT,
and it's just one of dozens that control the address remaps at the final layer —
all you have to do is poke them to make everything built on top topple. The
harder part then is keeping the platform up as the entirety of system memory is
scrambled underneath it.
The trick: be fast, and don't touch DRAM. Disable the APs, prime the
TLBs, warm the cache, disable interrupts, flush the target, serialize memory
accesses, and hope the CPU prefetched the upcoming instructions. Then rewire
the MCT/DCT to spaghettify DRAM, grab some data from the protected region,
revert the mappings, serialize again, enable interrupts, resume the APs, and
everything's back to normal, with the rest of the platform entirely unscathed.
With some careful setup of paging, cache states, threading, and the TLBs, the
address scrambling can be made to work from C, to illustrate the *p pipeline
collapsing, and the platform's corrupted view when suddenly &x != &x: