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Hot Chips 2026: Intel details cutting-edge tech in entry-level Wildcat Lake — value-focused 18A chips necessitated UCIe integration
Wildcat Lake is more advanced than it first appears.
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Intel's Wildcat Lake is unassuming, launching with the message that it was a cutting-edge alternative to the MacBook Neo with Intel's latest node and some trimmings around the edges. Although Wildcat Lake is, indeed, a budget part with major concessions to reach a market increasingly pushed to the side by powerful PC hardware, it also comes with a major innovation: UCIe.
The Universal Chiplet Interconnect Express (UCIe) specification first debuted in 2022, coincidentally around the time that planning around Wildcat Lake began. Both AMD and Intel have rallied behind UCIe as an open interconnect communications standard, though they've primarily relied on their own chiplet communication technology like AMD's Infinity Fabric. In Wildcat Lake, Intel leveraged UCIe to reduce cost. Further, it was a key technology that allowed Wildcat Lake to exist in the first place.
Opening the Hot Chips 2026 presentation, Intel's Lance Hacking, lead engineer on Wildcat Lake, said the company had the choice between a monolithic design or a basic, low-cost Multi-Chip Package (MCP). Intel has Foveros for advanced 2.5D and 3D packaging, but for a budget part like Wildcat Lake, that wasn't an option.
Choosing to leverage UCIe over an MCP design shaped the Wildcat Lake we have today, setting a roadmap for where Intel could cut compute to save cost and in areas where it would need to optimize to fit the necessary communication channels for the two chiplets.
As Hacking explained during his presentation, budget parts usually involve an N-1 design. You leverage older IP, trim around the edges to improve the economics of yields, and repackage it as a mainstream part. Wildcat Lake is different in that regard. It's taking Intel's latest, most advanced, and most expensive IP for compute and applying it to the budget domain.
With 18A at the center of the compute and ISMC's N6 handling the I/O die, Intel decided to make an MCP, which comes with some considerations. Advanced packaging allows designers to spend less die space on interconnects and use less power. With UCIe, Wildcat Lake's interconnect is 70% larger than that on Panther Lake, and even then, Intel says the change was worth it from a cost perspective.
Outside of space, power was the primary concern with using UCIe. Battery life, especially for a budget part meant to handle lighter workloads, is extremely important, and UCIe brings increased power demands. UCIe die-to-die is packetized, which led to a challenging design point, particularly around the display.